This disclosure relates generally to rate matching, and, more particularly, to a first-in first-out (FIFO) system that manages data writing and/or reading from a FIFO buffer using adaptive rate matching.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic devices, such as computers, network servers, televisions, portable phones, gaming devices, and the like, transmit and receive data. For example, a computer may download or upload files from a network server, or a television may download audio-video content from a content source. Data is also transmitted and received by internal components within electronic devices. In general, different electronic devices or different internal components of an electronic device may operate according to clock signals generated by different clock circuitry. Even if two different clock signals are meant to operate at the same frequency, it is possible for the clock signals to vary from one another, even if only very slightly. Yet even slight variations between two clock signals—which may be measured in parts-per-million—could result in lost data if data were transmitted directly between circuitry operating at different clock signals.
As such, a First-In First-Out (FIFO) storage system may be used to store the received data so that the first clock may send data independent of the second clock reading the data while still communicating all the desired data. However, FIFO controls may be statically set based on a range of possible parts-per-million (PPM) differences between the rate of data received and the rate of data read. For example, the PPM difference may be from design specifications of the first and second circuit. As such, these static FIFO settings may be based on the designs of the circuits, and so these FIFO settings may be selected to account for worst-case design scenarios, which may cause increased latency in communicating the data.